d flip-flop
英 [diː flɪp flɒp]
美 [diː flɪp flɑːp]
网络 D触发器
双语例句
- Design and Analysis of SEU/ SET Hardened D Flip-Flop
SEU/SET加固D触发器的设计与分析 - A New SEU Tolerant Satellite Dynamically-Reconfigurable System Based on SDR The Design of a SEE Hardened D Flip-Flop
抗单粒子翻转的可重构卫星通信系统一种抗单粒子全加固D触发器的设计 - Design of multi-valued double-edge-triggered D flip-flop based on clock-controlled neuron MOS transistor
基于钟控神经MOS管的多值双边沿D触发器设计时标触发器定时触发器 - Design of Set-Reset D Flip-Flop Using Resonant Tunneling 1-of-2 MUX
基于1-of-2共振隧穿数据选择器的可置位复位D触发器设计 - D latch and D flip-flop circuits using floating-gate MOS are designed. In order to introduce the application of D flip-flop, we design the register and counter by D flip-flops.
提出了基于浮栅MOS器件的D锁存器以及D触发器的电路设计，并以寄存器和计数器为例，介绍了D触发器的应用。 - Simulation results agree with the experiments. Finally, a frequency detection of a humidity sensor output with this D flip-flop differential frequency method is presented.
我们用软件仿真和试验结果验证了结论，并介绍了我们如何将D触发器差频方法用在湿度传感器的频率检测上。 - Design of low-power dynamic ternary CMOS D flip-flop
低功耗动态三值CMOSD触发器设计 - The flip-flop can more conveniently be transformed into JK flip-flop, D flip-flop, and T flip-flop.
这种触发器可以较方便地转换为JK触发器、D触发器和T触发器。 - Edge-triggered JK flip-flop Improved from D flip-flop
由D触发器改进的边沿JK触发器 - A Novel Dual Modulus Prescaler Based on New D Flip-Flop
基于新型D触发器的双模前置分频器 - In PLL design, dual-modulus prescaler is one of the bottlenecks in achieving a higher operation speed, and D flip-flop is the key factor limiting the speed of prescaler.
在锁相环设计中，双模前置分频器（dual-modulusprescaler）是一个速度瓶颈，而D触发器是限制其速度的主要因素。 - Research on short-circuit dissipation in master-slaver D flip-flop
主从型D触发器中短路功耗的研究 - According to double stable circuit which is constructed by two SET inverters, three R-S flip-flops are presented, and then putting forward D flip-flop.
在对由SET反相器构成的双稳态电路进行分析的基础上，提出了3种R＿S触发器，最终得出了D触发器。 - A Novel SEU-Hardened D Flip-Flop
一种新型的抗单粒子翻转的D触发器 - Two typical master-slave type D flip-flop of strong hardness to Single Event Upset ( SEU) for radiation environment are introduced.
介绍了两种已有的主从型边沿D触发器，它们具有很强的抗单粒子翻转能力。 - The D flip-flop employs a dynamic-loading structure and common-gate topology with single clock phase for the bias transistors.
D触发器单元采用动态负载结构，其偏置晶体管采用单时钟输入的共栅结构。 - After discussion of the data decision, the several structures of data-decision circuits used by D flip-flop were analyzed.
在讨论了数据判决的基本原理后，分析了利用D触发器实现的数据判决电路的几种结构。 - This flip-flop has correct logic function as a dynamic D flip-flop, and has the distinct advantage of simple structure, small chip area, and simple two-phase clock.
该触发器能很好地实现动态D触发器的逻辑功能，并且具有结构简单、芯片面积小、时钟简单等优点。 - In this paper a low-power dynamic ternary CMOS D flip-flop was designed, which is based on the dynamic CMOS ternary inverter having full voltage swings without DC power dissipations and is combined with the structure of a Simple Ternary Differential Logic ( STDL).
本文以一种没有直流功耗，具有完全电压摆幅的低功耗动态CMOS三值反相器作为基础，结合简单三值差分逻辑（STDL）的结构，设计了一种低功耗动态三值CMOSD触发器。 - To reduce power dissipation of D flip-flops by means of simplifying its configuration, a new design of semi-static D flip-flop is proposed.
本文从简化触发器内部锁存器结构以降低功耗的要求出发，提出了一种新型的半静态D触发器设计。 - Redundancy of CMOS circuits can be restrained by multithreshold CMOS, new pre-settable master-slave single-edge-triggered and double-edge-triggered D flip-flop based on multithreshold technique were designed.
本文利用多阈值技术实现电路的冗余抑制，设计了基于多阈值技术的CMOS可预置主从型单边沿、双边沿D触发器。 - From function equations of different kinds of flip-flop integrated circuits, we discussed the methods of function change from final product JK of D flip-flop to other kind in use.
从各种时钟触发器的特性方程出发，讨论了实际生产的集成时钟触发器JK型和D型向实用中可能使用的其他各类触发器转换的方法。 - Based on the circuit configuration of the D flip-flop and parameters of MOS transistors, the capacitances of the nodes inside the D flip-flop are calculated in this paper.
基于D触发器的电路结构与MOS管参数，本文对主从型D触发器各个节点电容进行了计算。 - Then we present a D master-slave flip-flop that consists of two ECL memory-gates.
提出了一种由两个ECL记忆门组成的ECL主从D触发器。 - Through analyzing its work principle, we find the method to raise the speed: use a novel CMOS dynamic D flip-flop and an improved synchronous frequency divider.
分析了双模前置分频器的工作原理，提出了提高其工作速度的方法，包括给出一种新型高速CMOS动态D触发器的设计以及同步分频器的改进。 - The characteristics of the body contact devices show the existence of floating effect. SPICE simulation of the circuit indicates that body resistance has obvious influence on the speed of BC ( body contact) D flip-flop circuit.
SPICE模拟表明体串联电阻对体接触SOI数字D触发器速度特性有明显的影响。 - The phase frequency detector ( PFD) circuit is constituted with the dynamic D flip-flop ( DFF) and the delay circuit can, which can effectively overcome the dead area, and have high-speed and low power consumption features.
鉴频鉴相器电路采用动态D触发器（DFF）和延迟电路构成，能有效克服死区，具有高速和低功耗的特点。 - The D flip-flop loop-based approach adopts a loop circuit formed by multiple shift registers and inverters, generating multiple square-wave signals of equal time-delay/ initial phase differences, which are then reshaped to sine waves via low-pass filtering.
基于D触发器环路的相控阵信号发生技术采用多个移位寄存器和反相器构成的环路，生成多路延时／初始相位等差的方波信号，再经低通滤波整形为正弦波。 - The effect of time-delay precision on the beamforming performance is also analyzed, and it is shown that when the clock frequency is high enough, it is feasible to combine multiple D flip-flop loops of different clock sources into a signal generator of even more channels.
论文还分析了信号延时精度对波束形成性能的影响，论证了时钟频率足够高时，把使用不同时钟源的多个D触发器环路合成具有更多通道数的装置是可行的。